A conventional DRAM (Dynamic Random Access Memory) memory cell is formed by associating a transistor and a capacitance for storing charges. More recently, a DRAM memory cell only consisting of one transistor has been proposed. This cell utilizes a floating channel effect for storing charges and does not require any additional capacitance.
Memory cells are conventionally laid out in a memory array so that the gates of the transistors of the cells laid out along a line of the memory array share a wordline, while the sources of the transistors of the cells laid out along a column of the memory array share a bitline. The stored datum in a memory cell may be accessed by means of a single row address represented by the wordline and of a single column address represented by the bitline.
Each word line is controlled via a wordline driver circuit, which is itself driven by a row address decoder.
In practice, the access transistor in the DRAM memory cell must have a very low leakage to sustain the information as long as possible. Its threshold voltage should thus be relatively high. This implies that a relatively large voltage has to be applied on the gate in order to make it conducting. It will be noted that the voltage of the wordline should also take into account the source-dependent change in the threshold voltage of the transistor of the memory cell known as “body effect”. The wordline driving the gate of the transistor should thus deliver a voltage which is typically 1.5 to 2 times higher than the nominal voltage.
Conventional wordline driver circuits are thus relatively bulky notably relatively to the size of a memory cell, which generally causes integration problems (notably the requirement for resorting to a stacking technique, a so-called “staggering” technique, for several driver circuits behind each other in order to address several adjacent lines of memory cells).
In FIG. 1, a wordline driver circuit 300 according to the state of the art is illustrated, as described in US patent application 2007/0109906.
The driver circuit 300 addresses a line of memory cells 100 via the wordline WL. All the nodes of the circuit 300 have a high voltage, except for the input signals Yi and Yi# from the line address decoder 330. The transistors of the driver circuit 300 thus have to support high voltages, notably the transistors 303 and 313.
By taking into account the different interconnections, the Applicant was able to estimate that the area of the driver circuit 300 of FIG. 1 corresponds to about 6 times that of transistor 303. Circuit 300 therefore proves to be particularly area consuming, notably as compared with the area of a memory cell formed with a single transistor.
The staggering of several driver circuits 300 behind each other then proves to be necessary in order to take into account the pitch difference.
A simpler wordline driver circuit is illustrated in FIGS. 2a and 2b. FIG. 2a illustrates the logic functions provided by this circuit, while FIG. 2b illustrates a possible embodiment thereof.
It will first of all be noted that this circuit includes two logic NOR gates 2, 3 in parallel, having a common input MWL# and having as another input, a single signal A or its complementary A#. The outputs are formed by local wordlines LWLE and LWL0.
It will then be noted that unlike the circuit of FIG. 1, the circuit of FIGS. 2a and 2b is supplied with a high voltage main wordline signal MWL# provided by a line address decoder 1. The result is more (about two to four times more) significant power consumption than for the circuit of FIG. 1.
An estimation made by the Applicant of the size of each of the transistors relatively to the reference W303 designating the width of the transistor 303 of FIG. 1 is reported on FIG. 2b. The result is that the total size is of the order of 6W303. Thus, the circuit of FIGS. 2a and 2b proves to be actually simpler than that of FIG. 1, nevertheless it remains area consuming.